ics650-44 mds 650-44 c 1 revision 080305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com spread spectrum clock synthesizer preliminary information description the ics650-44 is a spread spectrum clock synthesizer intended for video projector and digital tv applications. it generates three copies of an emi optimized 50 mhz clock signal (emi peak reduction of 7 to 14 db on 3rd through 19th harmonics) through the use of spread spectrum techniques from a 25 mhz crystal or clock input. the modulation rate is 50 khz. features ? packaged in 16-pin tssop (173 mil) ? supply voltages: vdd = 3.3 v, vddo = 2.5 v ? peak-to-peak jitter: 125 ps typ ? output duty cycle 45/55% (worst case) ? 25 mhz crystal or reference clock input ? zero (0) ppm frequency error on all output clocks ? advanced, low-power cmos process ? industrial temperature range (-40 to +85c) ? available in pb (lead) free package block diagram crystal osc gnd 2 3 vdd control logic 50m x2 25 mhz crystal or clock input external capacitors are required with a crystal input. x1/clkin 50m fs3:0 vddo pdts pll with spread spectrum 50m
spread spectrum clock synthesizer mds 650-44 c 2 revision 080305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com preliminary information ics650-44 pin assignment spread spectrum and output configuration table 12 1 11 2 10 x1/ clkin x2 3 9 fs0 4 fs1 vdd 5 50m 6 pdts 7 vdd 8 gnd fs2 vdd gnd vddo 50m 16 15 14 13 16-pin ( 173 mil) tssop 50m fs3 fs3 fs2 fs1 fs0 spread type ss out 0 0 0 0 center 0.25 0 0 0 1 center 0.50 0 0 1 0 center 0.75 0 0 1 1 center 1.00 0 1 0 0 center 1.25 0 1 0 1 center 1.50 0 1 1 0 center 1.75 0 1 1 1 center 2.00 1 0 0 0 down -0.5 1 0 0 1 down -0.75 1 0 1 0 down -1.0 1 0 1 1 down -1.25 1 1 0 0 down -1.5 1 1 0 1 down -1.75 1 1 1 0 down -2.0 1 1 1 1 off off
spread spectrum clock synthesizer mds 650-44 c 3 revision 080305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com preliminary information ics650-44 pin descriptions external components decoupling capacitor as with any high-performance mixed-signal ic, the ics650-44 must be isolated from system power supply noise to perform optimally. a decoupling capacitor of 0.01f must be connected between each vdd and the pcb ground plane. series termination resistor clock output traces over one inch should use series termination. to series terminate a 50 ? trace (a commonly used trace impedance), place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . crystal load capacitors the device crystal connections should include pads for small capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short pcb traces (and no vias) between the crystal and device. crystal capacitors must be connected from each of the pins x1 and x2 to ground. the value (in pf) of these crystal caps should equal (c l -6 pf)*2. in this equation, c l = crystal load capacitance in pf. example: for a crystal with a 16 pf load capacitance, each cryst al capacitor would be 20 pf [(16-6) x 2] = 20. pin number pin name pin type pin description 1 x1/clkin input crystal input. connect this pin to a 25 mhz crystal or external input clock. 2 fs0 input select pin 0. internal pull-up resistor. see table on page 2. 3 fs1 input select pin 1. internal pull-up resistor. see table on page 2. 4 50m output spread spectrum output. weak internal pull-down when tri-stated. 5 vdd power connect to +3.3 v. 6 gnd power connect to ground. 7 fs3 input select pin 3. internal pull-up resistor. see table on page 2. 8 50m output spread spectrum output. weak internal pull-down when tri-stated. 9 50m output spread spectrum output. weak internal pull-down when tri-stated. 10 vddo power connect to +2.5 v. 11 gnd power connect to ground. 12 vdd power connect to +3.3 v. 13 fs2 input select pin 2. internal pull-up resistor. see table on page 2. 14 pdts input powers down entire chip. tri-states clk outputs when low. internal pull-up. 15 vdd power connect to +3.3 v. 16 x2 output crystal output. connect this pin to a 25 mhz crystal. do not connect if clock input is used.
spread spectrum clock synthesizer mds 650-44 c 4 revision 080305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com preliminary information ics650-44 pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) the 0.01f decoupling capacitors should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between the decoupling capacitors and vdd pins. the pcb trace to vdd pins should be kept as short as possible, as should the pcb trace to the ground via. 2) the external crystal should be mounted just next to the device with short traces. the x1 and x2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) to minimize emi, the 33 ? series termination resistor should be placed close to the clock output. 4) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. other signal traces should be routed away from the ics650-44. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics650-44. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 5 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature (max. of 10 seconds) 260 c parameter min. typ. max. units ambient operating temperature -40 ? +85 c power supply voltage (vdd, with re spect to gnd) +3.135 +3.3 +3.465 v power supply voltage (vddo) +2.375 +2.5 +2.625 v power supply ramp time, figure 4 4 ms
spread spectrum clock synthesizer mds 650-44 c 5 revision 080305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com preliminary information ics650-44 dc electrical characteristics unless stated otherwise, vdd = 3.3 v 5%, vddo = 2.5 v 5% , ambient temperature -40 to +85 c parameter symbol conditions min. typ. max. units operating supply current idd no load 27 ma pdts = 0, no load 40 ua iddo no load 4 ma pdts = 0, no load 1 ua input high voltage v ih fs3:0, pdts 2v input low voltage v il fs3:0, pdts 0.8 v input high voltage v ih x1/clkin 0.7 x vdd v input low voltage v il x1/clkin 0.3 x vdd v output high voltage v oh i oh = -4 ma 1.8 v output low voltage v ol i ol = 4 ma 0.6 v short circuit current i os 50 ma nominal output impedance z o 20 ? internal pull-up resistor r pu fs3:0, pdts 360 k ? input leakage current i i fs3:0, pdts , vin=vdd 1 ua internal pull-down resistor r pd clk outputs 900 k ? input capacitance c in inputs 4 pf
spread spectrum clock synthesizer mds 650-44 c 6 revision 080305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com preliminary information ics650-44 ac electrical characteristics unless stated otherwise, vdd = 3.3 v 5%, vddo = 2.5 v 5% , ambient temperature -40 to +85 c note 1: measured with 5 pf load. parameter symbol conditions min. typ. max. units input frequency f in crystal or clock input 25 mhz spread spectrum modulation frequency 50 khz duty cycle t 2 /t 1 at vdd/2, note 1 and figures 1 and 2 45 50 55 % output fall time t 3 80% to 20%, note 1 and figures 1 & 3 1.5 ns output rise time t 4 20% to 80%, note 1 and figures 1 & 3 1.5 ns one sigma clock period jitter note 1 30 ps absolute jitter, peak-to-peak t ja deviation from mean, note1 & figures 1 and 6 125 ps output enable time t en pdts high to pll locked to within 1% of final value, figure 5 2.5 5 ms output disable time t dis pdts low to tri-state, figure 5 20 ns output-to-output skew 180 ps power-up time t p pll lock-time from power-up to 1% of final value, figure 4 610ms
spread spectrum clock synthesizer mds 650-44 c 7 revision 080305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com preliminary information ics650-44 thermal characteristics marking diagram marking diagram (pb free) notes: 1. ###### is the lot number. 2. yyww is the last two digits of the year and the week number that the part was assembled. 3. ?i? designates industrial temperature range. 4. ?l? designates pb (lead) free package. 5. bottom marking: (origin) origin = country of origin of not usa. parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 78 c/w ja 1 m/s air flow 70 c/w ja 3 m/s air flow 68 c/w thermal resistance junction to case jc 37 c/w 1 8 9 16 650gi-44 ###### yyww 1 8 9 16 650gi44l ###### yyww
spread spectrum clock synthesizer mds 650-44 c 8 revision 080305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com preliminary information ics650-44 timing diagrams figure 1: test and measurement setup figure 3: rise and fall time definitions figure 5: pdts to stable clock output timing figure 2: duty cycle definitions figure 4: power up and pll lock timing figure 6: short te rm jitter definition dut 0.01f c load vdds gnd outputs vddo t 3 clock output t 4 0v 80% of vddo 20% of vddo 1.25 v pdts clk outputs voh t en 0 v t dis 1% 1.25 v vddo t 2 clock t 1 0v 50% of vddo 4 ms 10 ms vdd 0v vdd 0v 0 ms power up time vco ramp time pll locked absolute jitter (p - p) mean value t ja
spread spectrum clock synthesizer mds 650-44 c 9 revision 080305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com preliminary information ics650-44 package outline and package dimensions (16-pin tssop, 173 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a "lf" su ffix to the part number are the pb-fr ee configuration and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature ics650gi-44 see page 7 tubes 16-pin tssop -40 to +85 c ICS650GI-44T tape and reel 16-pin tssop -40 to +85 c ics650gi-44lf see page 7 tubes 16-pin tssop -40 to +85 c ics650gi-44lft tape and reel 16-pin tssop -40 to +85 c index area 1 2 16 d e1 e seating plane a1 a a2 e - c - b aaa c c l millimeters inches symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa -- 0.10 -- 0.004
spread spectrum clock synthesizer mds 650-44 c 10 revision 080305 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com preliminary information ics650-44 revision history rev. originator date description of change - p. griffith 05/13/05 new proposal. a p. griffith 05/24/05 move from advance (proposal) to preliminary. added ics part number and lf. b p. griffith 06/14/05 added ?output-to -output skew? psec of 180 ps. c p. griffith 08/03/05 removed references to ss_en.
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